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IRS2184/IRS21844(S)PbF
The circuit shown in Figure 11 depicts a half bridge circuit with parasitic elements shown; Figures 12 and 13
show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic
inductances in the power circuit from the die bonding to the PCB tracks are lumped together in L C and L E
for each switch. When the high-side switch is on, V S1 is below the DC+ voltage by the voltage drops
associated with the power switch and the parasitic elements of the circuit. When the high-side power
switch turns off, the load current can momentarily flow in the low-side freewheeling diode due to the
inductive load connected to V S1, for instance (the load is not shown in these figures). This current flows
from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage
between V S1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the V S
pin).
DC+ BUS
L C1
DC+ BUS
+
V LC1
-
DC+ BUS
Q1
D1
Q1
Q1
D1
ON
OFF
Q2
V S1
L E1
L C2
D2
V S 1
Q2
OFF
+
V LE1
-
D2
I U
V S1
Q2
OFF
-
V LC 2
+
-
V D2
+
I U
-
L E2
V LE 2
+
DC- BUS
Figure 9: Parasitic Elements
DC- BUS
Figure 10: V s positive
DC- BUS
Figure 11: V s negative
In a typical power circuit, dV/dt is typically designed to be in the range of 1-5 V/ns. The negative V S
transient voltage can exceed this range during some events such as short circuit and over-current
shutdown, when di/dt is greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s
demanding applications. An indication of the IRS2184(4)’s robustness can be seen in Figure 14, where there
is represented the IRS2184(4) Safe Operating Area at V BS =15V based on repetitive negative V S spikes. A
negative V S transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage;
viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs
transients fall inside SOA.
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